Once a system design is created (components placed & connected), the system can be compiled by selecting Compile from either the File Menu or the Standard Toolbar. Compile analyzes the system design and indicates design errors if there are any. If there are no errors, Compile proceeds and allocates the required DSP resources.
Although Compile is an automatic process, certain settings can be pre-determined to help guide this process. Control blocks (i.e., those processing blocks that do not have audio inputs or outputs) can be Allocated To Unit, which assigns them to a particular Nexia device. This can be useful to dedicate particular control functions to specific physical locations, for example, to have all RCB devices wired to the same unit using a single cable.
Propagation Delay (also known as Latency) is an inherent time delay of the audio signals, which increases with the amount of DSP processing and NexLink routing applied. Each NexLink 'hop' (one-way transmission) produces 0.67mS delay. Therefore, system outputs can have different amounts of propagation delay. Compile determines worst-case propagation delay for a system, and applies Delay Equalization to synchronize all audio outputs. In applications where audio output synchronization is not important (audibly isolated areas), then Delay Equalization may be disabled on individual Input Output components (DSP blocks) or system wide. See Object Property Sheet and Compile Options.
For visual aids in determining DSP block allocations, see Display Options. A system design file must be compiled before it can be downloaded to NEXIA devices (see Send Configuration).
Compile results may be reviewed at any time (see Tools Menu > Layout Compile Results).
Example of Compile results for a simple system
see a list of possible Compile Error Messages